1. Field of the Invention
The present invention relates to a virtual ground type nonvolatile semiconductor memory device.
2. Description of the Related Art
A virtual ground type nonvolatile semiconductor memory including floating-gate nonvolatile memory cells has been suggested for realizing a high speed operation and low manufacturing cost (see JP-A-HEI3-176895).
A prior art virtual ground type nonvolatile semiconductor memory device includes a plurality of row lines, a plurality of column lines, and a plurality of nonvolatile memory cells each connected between two of the column lines. When reading data from a selected memory cell, the voltage at a row line connected to the selected memory cell is made high (=V.sub.CC), and the voltage at one column line connected to the selected memory cell is made low (=GND). Also, the other column line connected to the selected memory cell is connected to a data read circuit, thus detecting a read current flowing through the selected memory cell. In this case, leakage currents flow through non-selected memory cells. To reduce such leakage currents, a voltage is applied to a column line connected to one of the non-selected memory cells. This will be explained later in detail.
In the above-mentioned prior art virtual ground type nonvolatile semiconductor device, however, since a voltage is applied to a non-selected column line, a current flows through this non-selected column line to charge the parasitic capacity thereof, thus increasing the power consumption. Also, a power consumption is increased by an additional circuit being provided for generating such a voltage. Further, since the nonvolatile semiconductor device is of a multi-bit parallel output type which simultaneously outputs 8 bits, 16 bits or 32 bits, the provision of additional circuits further increases the power consumption and reduces the integration.